Semiconductors or integrated circuits (commonly called ICs, or chips) typically consist of multilevel structures. IC circuits fail due to various physical, chemical or mechanical mechanisms such as circular defects, electrical overstress, contamination, or wear out. Some failure analysis approaches and procedures require a die to be delayered down to a particular layer to locate such mechanisms. Methods of delayering a die involve mechanically abrading or polishing the die using a die holder, an abrasive, and a rotatable wheel.
Abrading and polishing the die are often problematic, time-consuming and limited in their usefulness. These problems and limitations result from instability, imprecision and lack of portability of abrading/polishing equipment. Abrading and polishing may damage underlying layers and undercut interconnect metal layers. The mechanical removal of layers can easily scratch, or embed polishing media or slurry into, underlying layers. Certain portions of the die may be abraded or polished at a faster rate, resulting in non-uniform abrading or polishing across the die. The abrading/polishing angle between the die surface and the rotatable wheel may be changed, resulting delayering only one corner of the die. While abrading and polishing the die, the die may break easily.
When more delayering is needed, the user places the die back onto the die holder for more delayering. This may introduce undesired variables in the die position, so that if the die is tilted differently or rotated from its position when previously delayered, the abrading/polishing produces undesired die surface characteristics. The lack of control results in undesired die surface characteristics, which can be detrimental to delayering analysis.
Another method for delayering the die is to use reactive ion etching. The method may produce non-planar etch results due to the in-homogeneity of the target layers. Reactive ion etching may require elevated temperatures, producing non-volatile species that can contaminate other layers.